Issue 
Wuhan Univ. J. Nat. Sci.
Volume 28, Number 3, June 2023



Page(s)  271  276  
DOI  https://doi.org/10.1051/wujns/2023283271  
Published online  13 July 2023 
Information Technology
CLC number: TM 464
HighPrecision DeadTime Intellectual Property Core and Its Compensation for Inverters
^{1}
College of Intelligent Systems Science and Engineering, Hubei Minzu University, Enshi 445000, Hubei, China
^{2}
College of Physical Science and Technology, Central China Normal University, Wuhan 430070, Hubei, China
^{†} To whom correspondence should be addressed. Email: liusanjunbox1@126.com
Received:
26
October
2023
In the inverter circuit, there exists a specific onoff time in each power transistor. As such, to prevent a short circuit of the two switch devices on the upper and lower bridge arms, a specific dead time must be set in the pulse width modulation (PWM) and the sinusoidal pulse width modulation (SPWM) signals. In this paper, an intellectual property (IP) core that can introduce a highprecision dead time of arbitrary length into PWM or SPWM signals of the inverter is designed to increase the precision, convenience and generalization of dead time control, resulting in a boosted control accuracy of up to 10 ns. Moreover, the added Avalon bus enables IP cores to be accessed by the field programmable gate array (FPGA) processor in a standard manner and multiple IP cores of the same class can be easily incorporated. In addition, an application for setting and compensating for dead time in a threephase inverter based on system on programmable chip (SOPC) technology is presented. With the Nios II CPU as its core, the system adopts the mean voltage compensation method to calculate the compensation voltage, and performs deadtime compensation in a feedforward manner. The three deadtime IP cores are controlled by Avalon bus. These allow the dead time of three groups of power transistors to be accurately controlled and flexibly adjusted. The system also features the master computer communication function while boasting the advantages of flexible control, high precision and low cost.
Key words: field programmable gate array (FPGA) / deadtime / sinusoidal pulse width modulation (SPWM)
Biography: CHEN Hao, male, Master candidate, research direction: power electronics, control technology of photovoltaic inverter. Email: chenhaobox1@163.com
Fundation item: Supported by the National Natural Science Foundation of China (61961016), the Natural Science Foundation of Hubei Province (2019CFB593) and PhD Research StartUp Foundation of Hubei Minzu University (MY2018B08)
© Wuhan University 2023
This is an Open Access article distributed under the terms of the Creative Commons Attribution License (https://creativecommons.org/licenses/by/4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
0 Introduction
The inverter is an essential device in photovoltaic power generation, wind power generation, and other technical applications and therefore possesses significant research value^{[1,2]}. An inverter can convert direct current (DC) to alternating current (AC). In practical applications, the power transistor in the main circuit of the inverter is not an ideal device. It is therefore necessary to set a period of dead time in its sinusoidal pulse width modulation (SPWM) or pulse width modulation (PWM) signal to ensure that the upper and lower power transistors of the same bridge arm are not turned on at the same time. The length of the dead time can have a significant impact: the upper and lower bridge arms' power devices are still subject to the risk of shorting out if the dead time is too short; the system will manifest obvious dead zone effects such as an increase in highorder harmonic amplitude and significant distortion if it is too long, thereby compromising the system's stability and effectiveness^{[3,4]}.
In light of the above considerations, the key to resolve the issue is to figure out how to perform deadtime compensation and generate appropriate dead time for the inverter's PWM and SPWM signals. Numerous studies have been conducted in this direction. Wan et al^{[5]} presented a generation method and a software compensation method of highfrequency dead time in inverters based on TMS320F2812. Ni et al^{[6]} proposed a pulsed deadtime compensation method, which can accurately compensate for the actual pulse in each switching cycle. Ding^{[7]} took the threephase halfbridge inverter circuit as the example and analyzed the shortcomings of the two traditional deadtime compensation strategies, namely current feedback and voltage feedback, along with designing a new deadtime compensation strategy based on digital signal processing (DSP). Zhang et al^{[8]} utilized the zerovoltageswitching (ZVT) technique to eliminate the blanking delay error, effectively reducing the total harmonic distortions (THDs) of the outputs.
The aforementioned literatures all assume a fixed inverter's dead time and finite dead time accuracy. By virtue of the highprecision adjustable dead time plan proposed in this article, the fixed dead time limit has been broken, and the user is allowed to set the dead time through the master computer in realtime. Besides, the system of this paper can achieve a dead time accuracy in the order of 10^{8}. To accomplish highly highprecision voltage compensation in realworld applications, the postinverter stage can fully incorporate the mean voltage feedforward compensation method.
In addition, this scheme makes use of a shift register to precisely delay the SPWM or PWM pulses using field programmable gate array (FPGA)based custom intellectual property (IP) core technology and transforms the PWM or SPWM pulses driving the inverter. The precise amount of the delay period is set by the Nios II CPU, which also controls the position of the extraction point using the C programming language for precise correction. Afterwards, a carefully constructed logic circuit generates pairs of SPWM and negated SPWM (or PWM and negated PWM) signals. The packed adjustable deadtime IP core offers the benefits of being simple to operate, highly precise, and simple to integrate into an FPGA system.
1 The Analysis of DeadTime Effect and DeadTime Precision
The onephase bridge arm of the inverter has two pairs of complementary power transistors which take a while to be turned on or off. As shown in Fig. 1, if T1 and T2 of the same bridge arm are turned off simultaneously, damage will be caused to the transistors.
Fig. 1 The influence of deadtime accuracy analysis 
Therefore, it is necessary to introduce a dead time when the driving signal is switched to ensure the safe operation of the power device. Despite being very short (usually a few microseconds), the dead time is incapable of affecting the performance of the system. Nevertheless, the building up of the deadtime effect of multiple consecutive cycles will cause the output voltage to contain a significant harmonic component, and the current waveform will be distorted^{[9,10]}.
The deadtime effect analysis is depicted in Fig. 2. Here, a threephase inverter is taken as an example. Setting the direction of the current flowing out of the switch tube of each phase as the positive direction, the error voltage caused by the dead time is given by
Fig. 2 Waveform analysis of deadtime effect ${I}_{n}$ is the phase current, ${S}_{\mathrm{i}\mathrm{1}}$ and ${S}_{\mathrm{i}\mathrm{2}}$ are the ideal driving signals of the same bridge arm, ${U}_{\mathrm{i}\mathrm{o}}$ is the ideal output voltage waveform, ${S}_{\mathrm{a}\mathrm{1}}$ and ${S}_{\mathrm{a}\mathrm{2}}$ are the actual driving signals, ${U}_{\mathrm{a}\mathrm{o}}$ is the actual output voltage waveform, ${U}_{\mathrm{b}\mathrm{u}\mathrm{s}}$ is the DC bus voltage and ${U}_{\mathrm{d}}$ is the deadtime voltage 
${U}_{\mathrm{d}n}=\mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}({i}_{n}){U}_{\mathrm{b}\mathrm{u}\mathrm{s}}\frac{{t}_{\mathrm{d}n}}{{T}_{\mathrm{s}}}$(1)
where $n\text{}(n=a,b,c)$ represents the three phases of A, B and C, respectively; ${U}_{\mathrm{b}\mathrm{u}\mathrm{s}}$ is the DC bus voltage; ${i}_{n}$ is the phase current; ${t}_{\mathrm{d}n}$ is the dead time; ${T}_{\mathrm{s}}$ is the switching period of power tubes.
The phase current satisfies the following equation:
$\{\begin{array}{l}\mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}\left({i}_{n}\right)=\mathrm{1},\hspace{1em}{i}_{n}>\mathrm{0}\\ \mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}\left({i}_{n}\right)=\mathrm{1},\hspace{1em}{i}_{n}<\mathrm{0}\end{array}$(2)
The vector calculation equation for the threephase voltage is as follows^{[11]}:
${U}_{\mathrm{d}}={U}_{\mathrm{d}a}+{U}_{\mathrm{d}b}{\mathrm{e}}^{\mathrm{j}\frac{\mathrm{2}}{\mathrm{3}}\mathrm{\pi}}+{U}_{\mathrm{d}c}{\mathrm{e}}^{\mathrm{j}\frac{\mathrm{4}}{\mathrm{3}}\mathrm{\pi}}$(3)
Substituting Eq. (1) into Eq. (3), the resultant error voltage vector caused by the threephase dead time can be derived to be
$\text{}{U}_{\mathrm{d}}=\frac{{U}_{\mathrm{b}\mathrm{u}\mathrm{s}}}{{T}_{\mathrm{s}}}\left({t}_{\mathrm{d}a}\mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}\left({i}_{a}\right)+{t}_{\mathrm{d}b}\mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}\left({i}_{b}\right){\mathrm{e}}^{\mathrm{j}\frac{\mathrm{2}}{\mathrm{3}}\mathrm{\pi}}\text{}+{t}_{\mathrm{d}c}\mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}\left({i}_{c}\right){\mathrm{e}}^{\mathrm{j}\frac{\mathrm{4}}{\mathrm{3}}\mathrm{\pi}}\right)$(4)
Hence, in the bipolar modulation mode, the deadtime voltage that needs to be compensated for in each switching period is given by
${U}_{\mathrm{c}n}=\mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}({i}_{n}){U}_{\mathrm{b}\mathrm{u}\mathrm{s}}\frac{\mathrm{2}{t}_{\mathrm{d}n}}{{T}_{\mathrm{s}}}$(5)
This compensating voltage is superimposed on the modulated wave voltage and is then compared with the carrier to obtain the SPWM signal.
Besides, the setting of a reasonable dead time should follow the principle of "turning off first before turning on". It ought to include the action delay time of the transistors^{[12]}. To maximally avoid the influence of the turnon and turnoff delay of the transistors on the waveform, the following considerations can be made. Taking phase of A as an example, the mean value of the switching function in one switching cycle can be expressed as
${S}_{\mathrm{d}}=\frac{{T}_{\mathrm{o}\mathrm{n}}{t}_{\mathrm{d}}{t}_{\mathrm{o}\mathrm{n}}+{t}_{\mathrm{o}\mathrm{f}\mathrm{f}}}{{T}_{\mathrm{s}}}\mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}({i}_{a})=(Dd)\mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}({i}_{a})$(6)
where ${T}_{\mathrm{o}\mathrm{n}}$ is turnon time in each switching period, ${t}_{\mathrm{o}\mathrm{n}}$ is the turnon delay of the transistor and ${t}_{\mathrm{o}\mathrm{f}\mathrm{f}}$ is the turnoff delay of the transistor. Since the switching frequency is much larger than the fundamental frequency when using SPWM, the modulating wave can be approximated as a constant within one switching period. As such, duty cycle $D$ of SPWM waves can be expressed in the amplitude of the triangular carrier ${V}_{\mathrm{t}\mathrm{r}\mathrm{i}}$ and the amplitude of the modulated wave ${V}_{\mathrm{m}\mathrm{o}\mathrm{d}}$, and it is given by
$D=\frac{\mathrm{1}}{\mathrm{2}}(\frac{{V}_{\mathrm{m}\mathrm{o}\mathrm{d}}}{{V}_{\mathrm{t}\mathrm{r}\mathrm{i}}}+\mathrm{1})$(7)
Combining Eqs. (6) and (7) yields the expression for the output voltage of the threephase system inverter:
$\{\begin{array}{l}{U}_{aN}=\frac{{U}_{\mathrm{b}\mathrm{u}\mathrm{s}}{V}_{\mathrm{m}\mathrm{o}\mathrm{d}}}{\mathrm{2}{V}_{\mathrm{t}\mathrm{r}\mathrm{i}}}\mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}({i}_{a}){U}_{\mathrm{b}\mathrm{u}\mathrm{s}}d\\ {U}_{bN}=\frac{{U}_{\mathrm{b}\mathrm{u}\mathrm{s}}{V}_{\mathrm{m}\mathrm{o}\mathrm{d}}}{\mathrm{2}{V}_{\mathrm{t}\mathrm{r}\mathrm{i}}}\mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}({i}_{b}){U}_{\mathrm{b}\mathrm{u}\mathrm{s}}d\\ {U}_{cN}=\frac{{U}_{\mathrm{b}\mathrm{u}\mathrm{s}}{V}_{\mathrm{m}\mathrm{o}\mathrm{d}}}{\mathrm{2}{V}_{\mathrm{t}\mathrm{r}\mathrm{i}}}\mathrm{s}\mathrm{i}\mathrm{g}\mathrm{n}({i}_{c}){U}_{\mathrm{b}\mathrm{u}\mathrm{s}}d\end{array}$(8)
According to Eq. (4), for a fixed dead time, the error voltage vector can only be six vectors based on the direction of the electric current. Hence, the error voltage is only six vectors. In other words, the accuracy of the resultant error voltage vector is governed by the accuracy of both the current direction and the dead time. Combined with Eq. (6) and Eq. (8), it is further understood that the accuracy of the deadtime voltages compensated by the three phases is determined by the accuracy of $d$, and the duty cycle of the equivalent dead time and the switch delay time is given by
$d=\frac{{t}_{\mathrm{d}}+{t}_{\mathrm{o}\mathrm{n}}{t}_{\mathrm{o}\mathrm{f}\mathrm{f}}}{{T}_{\mathrm{s}}}$(9)
This paper employs a highprecision FPGA to synthesize the dead time. By selecting a 100 MHz clock, the dead time can be adjusted within a reasonable range at 10 ns precision based on ${t}_{\mathrm{d}}=n\cdot {T}_{\mathrm{c}}$. Let the percentage change of deadtime voltage due to other factors be $E$, the required dead time be ${t}_{\mathrm{d}\mathrm{r}}$ ,and the actual dead time set be ${t}_{\mathrm{d}\mathrm{a}}$, then the relative percentage error of the actual deadtime voltage ${R}_{\mathrm{e}\mathrm{U}}$ is given by
${R}_{\mathrm{e}\mathrm{U}}=\frac{\left{t}_{\mathrm{d}\mathrm{r}}{t}_{\mathrm{d}\mathrm{a}}\right}{{t}_{\mathrm{d}\mathrm{r}}}\times \frac{\mathrm{1}}{E}\times \mathrm{100}\mathrm{\%}$(10)
The deadtime accuracy of 10, 15, 30 and 50 ns is analyzed in MATLAB, under the assumption of a required dead time between 300 and 350 ns and the $\mathrm{1}/E$ value in the range of 0.998 to 1.002. The results are presented in Fig. 3. It can be inferred that the lower the deadtime accuracy, the lower the relative error percentage of the deadtime voltage. Besides, for relatively high deadtime accuracy, the relative error percentage of deadtime voltage demonstrates apparent changes.
Fig. 3 The influence of deadtime accuracy analysis 
2 The Design of DeadTime IP Core
In order to realize the dynamic adjustment of dead time of a threephase inverter, this paper takes full advantage of the system on programmable chip (SOPC) technology. One of the most prominent features of SOPC technology is the possibility of hardware design in software, in which common functional modules that can be directly controlled by Nios II CPU correspond to specific IP cores. Users are able to customize the IP core to achieve the intended function^{[13]}. In this paper, an adjustable highprecision deadtime IP core is customized whose structure is outlined in Fig. 4.
Fig. 4 Overall structure of the deadtime IP core 
The IP core is mainly composed of an Avalon read/write control logic module, a delay shift register group module, a delay time register, a start control register and a dead time generation and control logic unit. It can introduce a dead time within the precision range to the input PWM or SPWM signal. Taking the input SPWM signal as an example, after being injected at SPWM_in port, the signal first undergoes a delay operation through the delay shift register group to obtain the SPWM_delay signal.
Suppose there are $N$ shift registers in the delay shift register group, each with the same system clock cycle ${T}_{\mathrm{c}}$, and assume that the SPWM_delay signal is set by the Avalon read/write control logic to fetch from the output of the nth shift register, then the delay time of SPWM_delay signal relative to the SPWM_in signal is $n\cdot {T}_{\mathrm{c}}$. Apparently, $N\cdot {T}_{\mathrm{c}}$ is the largest delay time difference and ${T}_{\mathrm{c}}$ reflects the accuracy of the delay time. Specifically, in the hardware description language of the IP core, a macro definition of N can be made to achieve a sufficiently long delay time.
The data runs in the form of continuous flow in the delayed shift register. Concretely, on the rising edge (or falling edge) of each clock, the $k$th ($k$ is an integer, $\mathrm{1}<k<N$) register reads the data in the $(k\mathrm{1})$th register and transmits its own stored data to the $(k+\mathrm{1})$th register. The details are illustrated in Fig. 5. In addition, the system defines the delay time register as a 32bit unsigned integer. There is also logic in the delay shift register group module to make the PWM_delay signal fetch the data from the d_data[n] register. The Nios II processor writes the value n to set the specific delay time.
Fig. 5 Logic details of the deadtime IP core 
The names of the delay time register and the start control register in the IP core are delay_num_reg and start_reg respectively. Any integer value $n$ can be written into the delay time register through the Avalon bus to control the length of the dead time and write control commands into the start control register to dictate the start and stop of the IP core by the Nios II CPU. The process of the read/write control logic is as follows:
reg [31:0] delay_num_reg;
reg [31:0] start_reg;
always @(posedge clk)
if((CPU_CS==1)&&(CPU_WR==1)&&(CPU_Addr==0))
delay_num_reg<=CPU_WR_DATA;
always@(posedge clk)
if((CPU_CS==1)&&(CPU_WR==1)&&(CPU_Addr==1))
start_reg<=CPU_WR_DATA;
In addition, the input signal of the dead time generation logic contains PWM_in, PWM_delay, and start_reg[0], whereas the output signal contains PWM_out and PWM_out_not. Specifically, the logical relationship between the output and the input is given by:
assign PWM_out=(start_reg[0]==1)?(PWM &PWM_
delay):0;
assign PWM_out_not=(start_reg[0]==1)?( ~(PWM
PWM_delay)):0;
As detailed in Fig. 6, this paper carries out the deadtime IP core function test in Modelsim. The reference clock runs at 100 MHz. The last two signals are the finally generated SPWM signals within the dead time which is set arbitrarily with 10 ns steps under the maximum value. It can be seen from the simulation results that the function of the custom deadtime IP core meets the requirements, with nanosecond accuracy of the dead time.
Fig. 6 Simulation of the deadtime IP core in Modelsim 
3 Compensation of DeadTime IP Core in ThreePhase Inverter
The dead time of each of the three bridge arms of a threephase inverter can be independently altered and the appropriate deadtime compensation voltage can be obtained using the approach presented in this paper. A threephase inverter circuit with six Insulated Gate Bipolar Transistors (IGBTs) is shown in the following example. In order to successfully control the six IGBTs of the three bridge arms on the inverter, this paper leverages three custom dead time generation IP cores to generate six control signals, and the Nios II CPU communicates with the three IP cores through the Avalon bus. The specific control structure is diagrammed in the Fig. 7.
Fig. 7 System structure of a threephase inverter within the deadtime IP core 
The entire system entails a threephase inverter circuit, a sampling circuit, a modulator circuit and a FPGA part. It is known that a reasonable dead time of each IGBT is between 0.5 and 1.2 μs. The dead time of the SPWM signal can be set within the accuracy of 10 ns by the master computer. Moreover, after the threephase current is sampled by the sampling circuit, the current data is transmitted to the current direction calculation module built in the FPGA system. According to Eq. (5), the deadtime voltage will be calculated in real time, before the modified SPWM signal is generated by the modulator module.
Furthermore, the names of the three deadtime IP cores added to the SOPC system are dzt1, dzt2 and dzt3 respectively. Taking dzt1 as an example, its base address in the FPGA development environment (i.e., Nios II Software Build Tools for Eclipse) is DZT1_BASE. With the assumption that the dead time of dzt1 is x μs, the C program language to be applied is as follows:
n1=(unsigned int)(x*1000/10);
IOWR_32DIRECT(DZT1_BASE, 0, n1);
IOWR_32DIRECT(DZT1_BASE, 4, 1);
4 Conclusion
In this paper, the design of an IP core capable of generating highprecision adjustable dead time for SPWM and PWM pulses based on FPGA is presented, along with a practical scheme for threephase inverter circuit control and deadtime compensation using the dead time IP core. By encapsulating IP cores and customizing peripherals in SOPC technology, not only can the dead time be set to nanosecond accuracy thereby resolving the dead time effect, but the overall running speed and stability of the FPGAbased inverter system are also boosted. These improvements will allow users to build SOPC systems with dead time settings for multiple IGBTs or MOSFETs.
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All Figures
Fig. 1 The influence of deadtime accuracy analysis 

In the text 
Fig. 2 Waveform analysis of deadtime effect ${I}_{n}$ is the phase current, ${S}_{\mathrm{i}\mathrm{1}}$ and ${S}_{\mathrm{i}\mathrm{2}}$ are the ideal driving signals of the same bridge arm, ${U}_{\mathrm{i}\mathrm{o}}$ is the ideal output voltage waveform, ${S}_{\mathrm{a}\mathrm{1}}$ and ${S}_{\mathrm{a}\mathrm{2}}$ are the actual driving signals, ${U}_{\mathrm{a}\mathrm{o}}$ is the actual output voltage waveform, ${U}_{\mathrm{b}\mathrm{u}\mathrm{s}}$ is the DC bus voltage and ${U}_{\mathrm{d}}$ is the deadtime voltage 

In the text 
Fig. 3 The influence of deadtime accuracy analysis 

In the text 
Fig. 4 Overall structure of the deadtime IP core 

In the text 
Fig. 5 Logic details of the deadtime IP core 

In the text 
Fig. 6 Simulation of the deadtime IP core in Modelsim 

In the text 
Fig. 7 System structure of a threephase inverter within the deadtime IP core 

In the text 
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