Open Access
Wuhan Univ. J. Nat. Sci.
Volume 28, Number 3, June 2023
Page(s) 271 - 276
Published online 13 July 2023

© Wuhan University 2023

Licence Creative CommonsThis is an Open Access article distributed under the terms of the Creative Commons Attribution License (, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

0 Introduction

The inverter is an essential device in photovoltaic power generation, wind power generation, and other technical applications and therefore possesses significant research value[1,2]. An inverter can convert direct current (DC) to alternating current (AC). In practical applications, the power transistor in the main circuit of the inverter is not an ideal device. It is therefore necessary to set a period of dead time in its sinusoidal pulse width modulation (SPWM) or pulse width modulation (PWM) signal to ensure that the upper and lower power transistors of the same bridge arm are not turned on at the same time. The length of the dead time can have a significant impact: the upper and lower bridge arms' power devices are still subject to the risk of shorting out if the dead time is too short; the system will manifest obvious dead zone effects such as an increase in high-order harmonic amplitude and significant distortion if it is too long, thereby compromising the system's stability and effectiveness[3,4].

In light of the above considerations, the key to resolve the issue is to figure out how to perform dead-time compensation and generate appropriate dead time for the inverter's PWM and SPWM signals. Numerous studies have been conducted in this direction. Wan et al[5] presented a generation method and a software compensation method of high-frequency dead time in inverters based on TMS320F2812. Ni et al[6] proposed a pulsed dead-time compensation method, which can accurately compensate for the actual pulse in each switching cycle. Ding[7] took the three-phase half-bridge inverter circuit as the example and analyzed the shortcomings of the two traditional dead-time compensation strategies, namely current feed-back and voltage feedback, along with designing a new dead-time compensation strategy based on digital signal processing (DSP). Zhang et al[8] utilized the zero-voltage-switching (ZVT) technique to eliminate the blanking delay error, effectively reducing the total harmonic distortions (THDs) of the outputs.

The aforementioned literatures all assume a fixed inverter's dead time and finite dead time accuracy. By virtue of the high-precision adjustable dead time plan proposed in this article, the fixed dead time limit has been broken, and the user is allowed to set the dead time through the master computer in real-time. Besides, the system of this paper can achieve a dead time accuracy in the order of 10-8. To accomplish highly high-precision voltage compensation in real-world applications, the post-inverter stage can fully incorporate the mean voltage feedforward compensation method.

In addition, this scheme makes use of a shift register to precisely delay the SPWM or PWM pulses using field programmable gate array (FPGA)-based custom intellectual property (IP) core technology and transforms the PWM or SPWM pulses driving the inverter. The precise amount of the delay period is set by the Nios II CPU, which also controls the position of the extraction point using the C programming language for precise correction. Afterwards, a carefully constructed logic circuit generates pairs of SPWM and negated SPWM (or PWM and negated PWM) signals. The packed adjustable dead-time IP core offers the benefits of being simple to operate, highly precise, and simple to integrate into an FPGA system.

1 The Analysis of Dead-Time Effect and Dead-Time Precision

The one-phase bridge arm of the inverter has two pairs of complementary power transistors which take a while to be turned on or off. As shown in Fig. 1, if T1 and T2 of the same bridge arm are turned off simultaneously, damage will be caused to the transistors.

thumbnail Fig. 1

The influence of dead-time accuracy analysis

Therefore, it is necessary to introduce a dead time when the driving signal is switched to ensure the safe operation of the power device. Despite being very short (usually a few microseconds), the dead time is incapable of affecting the performance of the system. Nevertheless, the building up of the dead-time effect of multiple consecutive cycles will cause the output voltage to contain a significant harmonic component, and the current waveform will be distorted[9,10].

The dead-time effect analysis is depicted in Fig. 2. Here, a three-phase inverter is taken as an example. Setting the direction of the current flowing out of the switch tube of each phase as the positive direction, the error voltage caused by the dead time is given by

thumbnail Fig. 2

Waveform analysis of dead-time effect

is the phase current, and are the ideal driving signals of the same bridge arm, is the ideal output voltage waveform, and are the actual driving signals, is the actual output voltage waveform, is the DC bus voltage and is the dead-time voltage


where represents the three phases of A, B and C, respectively; is the DC bus voltage; is the phase current; is the dead time; is the switching period of power tubes.

The phase current satisfies the following equation:


The vector calculation equation for the three-phase voltage is as follows[11]:


Substituting Eq. (1) into Eq. (3), the resultant error voltage vector caused by the three-phase dead time can be derived to be


Hence, in the bipolar modulation mode, the dead-time voltage that needs to be compensated for in each switching period is given by


This compensating voltage is superimposed on the modulated wave voltage and is then compared with the carrier to obtain the SPWM signal.

Besides, the setting of a reasonable dead time should follow the principle of "turning off first before turning on". It ought to include the action delay time of the transistors[12]. To maximally avoid the influence of the turn-on and turn-off delay of the transistors on the waveform, the following considerations can be made. Taking phase of A as an example, the mean value of the switching function in one switching cycle can be expressed as


where is turn-on time in each switching period, is the turn-on delay of the transistor and is the turn-off delay of the transistor. Since the switching frequency is much larger than the fundamental frequency when using SPWM, the modulating wave can be approximated as a constant within one switching period. As such, duty cycle of SPWM waves can be expressed in the amplitude of the triangular carrier and the amplitude of the modulated wave , and it is given by


Combining Eqs. (6) and (7) yields the expression for the output voltage of the three-phase system inverter:


According to Eq. (4), for a fixed dead time, the error voltage vector can only be six vectors based on the direction of the electric current. Hence, the error voltage is only six vectors. In other words, the accuracy of the resultant error voltage vector is governed by the accuracy of both the current direction and the dead time. Combined with Eq. (6) and Eq. (8), it is further understood that the accuracy of the dead-time voltages compensated by the three phases is determined by the accuracy of , and the duty cycle of the equivalent dead time and the switch delay time is given by


This paper employs a high-precision FPGA to synthesize the dead time. By selecting a 100 MHz clock, the dead time can be adjusted within a reasonable range at 10 ns precision based on . Let the percentage change of dead-time voltage due to other factors be , the required dead time be ,and the actual dead time set be , then the relative percentage error of the actual dead-time voltage is given by


The dead-time accuracy of 10, 15, 30 and 50 ns is analyzed in MATLAB, under the assumption of a required dead time between 300 and 350 ns and the value in the range of 0.998 to 1.002. The results are presented in Fig. 3. It can be inferred that the lower the dead-time accuracy, the lower the relative error percentage of the dead-time voltage. Besides, for relatively high dead-time accuracy, the relative error percentage of dead-time voltage demonstrates apparent changes.

thumbnail Fig. 3

The influence of dead-time accuracy analysis

2 The Design of Dead-Time IP Core

In order to realize the dynamic adjustment of dead time of a three-phase inverter, this paper takes full advantage of the system on programmable chip (SOPC) technology. One of the most prominent features of SOPC technology is the possibility of hardware design in software, in which common functional modules that can be directly controlled by Nios II CPU correspond to specific IP cores. Users are able to customize the IP core to achieve the intended function[13]. In this paper, an adjustable high-precision dead-time IP core is customized whose structure is outlined in Fig. 4.

thumbnail Fig. 4

Overall structure of the dead-time IP core

The IP core is mainly composed of an Avalon read/write control logic module, a delay shift register group module, a delay time register, a start control register and a dead time generation and control logic unit. It can introduce a dead time within the precision range to the input PWM or SPWM signal. Taking the input SPWM signal as an example, after being injected at SPWM_in port, the signal first undergoes a delay operation through the delay shift register group to obtain the SPWM_delay signal.

Suppose there are shift registers in the delay shift register group, each with the same system clock cycle , and assume that the SPWM_delay signal is set by the Avalon read/write control logic to fetch from the output of the nth shift register, then the delay time of SPWM_delay signal relative to the SPWM_in signal is . Apparently, is the largest delay time difference and reflects the accuracy of the delay time. Specifically, in the hardware description language of the IP core, a macro definition of N can be made to achieve a sufficiently long delay time.

The data runs in the form of continuous flow in the delayed shift register. Concretely, on the rising edge (or falling edge) of each clock, the -th ( is an integer, ) register reads the data in the -th register and transmits its own stored data to the -th register. The details are illustrated in Fig. 5. In addition, the system defines the delay time register as a 32-bit unsigned integer. There is also logic in the delay shift register group module to make the PWM_delay signal fetch the data from the d_data[n] register. The Nios II processor writes the value n to set the specific delay time.

thumbnail Fig. 5

Logic details of the dead-time IP core

The names of the delay time register and the start control register in the IP core are delay_num_reg and start_reg respectively. Any integer value can be written into the delay time register through the Avalon bus to control the length of the dead time and write control commands into the start control register to dictate the start and stop of the IP core by the Nios II CPU. The process of the read/write control logic is as follows:

reg [31:0] delay_num_reg;

reg [31:0] start_reg;

always @(posedge clk)



always@(posedge clk)



In addition, the input signal of the dead time generation logic contains PWM_in, PWM_delay, and start_reg[0], whereas the output signal contains PWM_out and PWM_out_not. Specifically, the logical relationship between the output and the input is given by:

assign PWM_out=(start_reg[0]==1)?(PWM &PWM_


assign PWM_out_not=(start_reg[0]==1)?( ~(PWM|


As detailed in Fig. 6, this paper carries out the dead-time IP core function test in Modelsim. The reference clock runs at 100 MHz. The last two signals are the finally generated SPWM signals within the dead time which is set arbitrarily with 10 ns steps under the maximum value. It can be seen from the simulation results that the function of the custom dead-time IP core meets the requirements, with nanosecond accuracy of the dead time.

thumbnail Fig. 6

Simulation of the dead-time IP core in Modelsim

3 Compensation of Dead-Time IP Core in Three-Phase Inverter

The dead time of each of the three bridge arms of a three-phase inverter can be independently altered and the appropriate dead-time compensation voltage can be obtained using the approach presented in this paper. A three-phase inverter circuit with six Insulated Gate Bipolar Transistors (IGBTs) is shown in the following example. In order to successfully control the six IGBTs of the three bridge arms on the inverter, this paper leverages three custom dead time generation IP cores to generate six control signals, and the Nios II CPU communicates with the three IP cores through the Avalon bus. The specific control structure is diagrammed in the Fig. 7.

thumbnail Fig. 7

System structure of a three-phase inverter within the dead-time IP core

The entire system entails a three-phase inverter circuit, a sampling circuit, a modulator circuit and a FPGA part. It is known that a reasonable dead time of each IGBT is between 0.5 and 1.2 μs. The dead time of the SPWM signal can be set within the accuracy of 10 ns by the master computer. Moreover, after the three-phase current is sampled by the sampling circuit, the current data is transmitted to the current direction calculation module built in the FPGA system. According to Eq. (5), the dead-time voltage will be calculated in real time, before the modified SPWM signal is generated by the modulator module.

Furthermore, the names of the three dead-time IP cores added to the SOPC system are dzt1, dzt2 and dzt3 respectively. Taking dzt1 as an example, its base address in the FPGA development environment (i.e., Nios II Software Build Tools for Eclipse) is DZT1_BASE. With the assumption that the dead time of dzt1 is x μs, the C program language to be applied is as follows:

n1=(unsigned int)(x*1000/10);



4 Conclusion

In this paper, the design of an IP core capable of generating high-precision adjustable dead time for SPWM and PWM pulses based on FPGA is presented, along with a practical scheme for three-phase inverter circuit control and dead-time compensation using the dead time IP core. By encapsulating IP cores and customizing peripherals in SOPC technology, not only can the dead time be set to nanosecond accuracy thereby resolving the dead time effect, but the overall running speed and stability of the FPGA-based inverter system are also boosted. These improvements will allow users to build SOPC systems with dead time settings for multiple IGBTs or MOSFETs.


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All Figures

thumbnail Fig. 1

The influence of dead-time accuracy analysis

In the text
thumbnail Fig. 2

Waveform analysis of dead-time effect

is the phase current, and are the ideal driving signals of the same bridge arm, is the ideal output voltage waveform, and are the actual driving signals, is the actual output voltage waveform, is the DC bus voltage and is the dead-time voltage

In the text
thumbnail Fig. 3

The influence of dead-time accuracy analysis

In the text
thumbnail Fig. 4

Overall structure of the dead-time IP core

In the text
thumbnail Fig. 5

Logic details of the dead-time IP core

In the text
thumbnail Fig. 6

Simulation of the dead-time IP core in Modelsim

In the text
thumbnail Fig. 7

System structure of a three-phase inverter within the dead-time IP core

In the text

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